شناسه محصول: GAL16V8D-PLCC20 دسته: برچسب: , ,

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توضیحات محصول

Low Voltage E2CMOS PLD Generic Array Logic

The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.


high performance e2cmos® technology
– 3.5 ns maximum propagation delay
– fmax = 250 mhz
– 3.0 ns maximum from clock input to data output
– ultramos® advanced cmos technology
50% to 75% reduction in power from bipolar
– 75ma typ icc on low power device
– 45ma typ icc on quarter power device
active pull-ups on all pins
eight output logic macrocells
– maximum flexibility for complex logic designs
– programmable output polarity
– also emulates 20-pin pal® devices with full function/fuse map/parametric compatibility
preload and power-on reset of all registers
– 100% functional testability
electronic signature for identification

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