High Performance RISC CPU: C Compiler optimized architecture/instruction set Data EEPROM to 1024 bytes Linear program memory addressing to 64 Kbytes Linear data memory addressing to 4 Kbytes Up to 16 MIPS operation 16-bit wide instructions, 8-bit wide data path Priority levels for interrupts 31-level, software accessible hardware stack 8 x 8 Single-Cycle Hardware Multiplier …
ادامه خواندنPIC18F46K22-I/P PDIP